The present invention generally relates to memory devices for use with computers and other processing apparatuses. More particularly, this invention relates to high capacity non-volatile or permanent memory-based mass storage devices of the type known as solid state drives (SSD).
Mass storage devices such as advanced technology (ATA) or small computer system interface (SCSI) drives are rapidly adopting non-volatile memory technology such as flash memory or other emerging solid state memory technology, including phase change memory (PCM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferromagnetic random access memory (FRAM), organic memories, or nanotechnology-based storage media such as carbon nanofiber/nanotube-based substrates. Currently the most common technology uses NAND flash memory as inexpensive storage memory.
Current solid state drives are limited in their capacity by the density of the NAND chips in conjunction with the limitations of the control logic, that is, the memory controller. Even if the memory management unit is aware of a large memory space through, for example, a 48-bit large block addressing scheme, the actual controller will typically have limitations in the number of address lines or chip-enable lines, which then limits the overall capacity of the device to a much smaller size. For example, using an eight-channel interleaved flash memory controller and 32 Gbit ICs, the maximum capacity of a single unit solid state drive is currently 256 GB.
In the past, the cost of NAND flash memory was prohibitive for even considering ultra-high capacity solid state drives, but with production ramping up and NAND cost decreasing on average by 50% per year, solid state drives have not only gained acceptance in the market but are also constantly increasing in capacity. Decreasing acquisition cost in conjunction with much lower power consumption (low operational cost) results in a lower total cost of ownership (TCO). The lower TCO combined with the mechanical robustness of solid state drives have created a need for a type of solid state drive with ultra high capacity.
Current solutions to overcome the size limitations posed by limited density of NAND flash memory ICs and the limited number of chip select lines on the controller employ bundling of several solid state drives within a single package and functionally integrating them into a spanned volume or into a striped RAID array (Level 0). An example of such a solid state drive 10 is schematically represented in FIG. 1, which shows a printed circuit board 12 equipped with a power and data connector 14 and multiple memory chips 18. The connector 14 provides a system interface by which the solid state drive 10 can be connected to a cable of a host computer system (not shown). The memory chips 18 are typically flash (e.g., NAND) non-volatile memory chips or another non-volatile memory technology. FIG. 1 further represents the capacity of the solid state drive 10 as increased by effectively consolidating two separate solid state drives on the circuit board 12, represented as two separate arrays (banks) 16 of the memory chips 18, each with a dedicated control logic (controller) 20 (represented as an integrated circuit (IC) chip), and further interfaced with the computer system through a RAID controller 22, typically through a Level 0 striped configuration.
The type of configuration represented in FIG. 1 has the advantage of ease of configurability and, in most cases, allows some additional management features such as the selection of the type of array, meaning JBOD, RAID Level 0 or RAID Level 1 (striping or mirroring, respectively). On the downside, this arrangement incurs the additional cost for the RAID controller 22 as well as the second solid state drive controller 20, typically a Serial ATA (SATA) to NAND flash memory controller, with an extra volatile cache (not shown). Functionally, the RAID 0, as the most commonly used, will not be able to play out the combined transfer rates of two drives because the system interface (connector 14) is usually a single SATA link, which limits the host transfer rate and can cause some problems if the combined internal media transfer rate at the back-end of the solid state drive 10 is greater than the host transfer rate.
Another important aspect for performance of a solid state drive is the discrepancy in speed between contemporary controllers at the front end of the solid state drive and the NAND flash storage memory at the back-end of the drive. NAND flash is inherently slow because of its architecture and design limitations whereas flash controllers can be scaled up to outpace the performance of the memory components by multiples.